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this is information on a product in full production. april 2013 docid4997 rev 13 1/33 1 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 16-kbit, 8-kbit, 4-kbit, 2-kbit and 1-kbit (8-bit or 16-bit wide) mi crowire serial access eeprom datasheet - production data features ? industry standard microwire bus ? single supply voltage: ? 4.5 v to 5.5 v for m93cx6 ? 2.5 v to 5.5 v for m93cx6-w ? 1.8 v to 5.5 v for m93cx6-r ? dual organization: by word (x16) or byte (x8) ? programming instructions that work on: byte, word or entire memory ? self-timed programming cycle with auto-erase: 5 ms ? ready/busy signal during programming ? 2 mhz clock rate ? sequential read operation ? enhanced esd/latch-up behavior ? more than 1 million write cycles ? more than 40 year data retention ? packages ? so8, tssop8, ufdfpn8 packages: rohs-compliant and halogen-free (ecopack2?) ? pdip8 package: rohs-compliant (ecopack1?) pdip8 (bn) so8 (mn) 150 mil width tssop8 (dw) 169 mil width ufdfpn8 (mc) 2 x 3 mm table 1. device summary reference part number memory size supply voltage m93c46xx m93c46 1 kbit 4.5 v to 5.5 v m93c46-w 2.5 v to 5.5 v m93c56xx m93c56 2 kbit 4.5 v to 5.5 v m93c56-w 2.5 v to 5.5 v m93c56-r 1.8 v to 5.5 v m93c66xx m93c66 4 kbit 4.5 v to 5.5 v m93c66-w 2.5 v to 5.5 v m93c66-r 1.8 v to 5.5 v m93c76xx m93c76-w 8 kbit 2.5 v to 5.5 v m93c76-r 1.8 v to 5.5 v m93c86xx m93c86 16 kbit 4.5 v to 5.5 v m93c86-w 2.5 v to 5.5 v www.st.com
contents m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 2/33 docid4997 rev 13 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.3 power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 read data from memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 erase and write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.1 write enable and write disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.2 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.3 write all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.4 erase byte or word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.5 erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6ready/busy status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid4997 rev 13 3/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx contents 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of tables m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 4/33 docid4997 rev 13 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. instruction set for the m93c46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. instruction set for the m93c56 and m93c66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. instruction set for the m93c76 and m93c86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. operating conditions (m93cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. operating conditions (m93cx6-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. operating conditions (m93cx6-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. ac measurement conditions (m93cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. ac measurement conditions (m93cx6-w and m93cx6 -r) . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 14. dc characteristics (m93cx6, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 15. dc characteristics (m93cx6-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 16. dc characteristics (m93cx6-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 17. ac characteristics (m93cx6, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 18. ac characteristics (m93cx6-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. ac characteristics (m93cx6-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 20. pdip8 ? 8 lead plastic dual in-line package, 300 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . 28 table 22. ufdfpn8 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 23. tssop8 ? 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 30 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 25. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
docid4997 rev 13 5/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx list of figures list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. read, write, wen, wd s sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. wral sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. erase, eral sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. write sequence with one clock g litch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. ac testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. synchronous timing (start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. synchronous timing (read or writ e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. synchronous timing (read or writ e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. pdip8 ? 8 lead plastic dual in-line package, 300 mils body width, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. ufdfpn8 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. tssop8 ? 8 lead thin shrink small outline, pack age outline . . . . . . . . . . . . . . . . . . . . . . . 30
description m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 6/33 docid4997 rev 13 1 description the m93c46 (1 kbit), m93c56 (2 kbit), m93c66 (4 kbit), m93c76 (8 kbit) and m93c86 (16 kbit) are electrica lly erasable programmable memo ry (eeprom) de vices accessed through the microwire bus protocol. the memory array can be configured either in bytes (x8b) or in words (x16b). the m93cx6 devices operate within a voltage supply range from 4.5 v to 5.5 v, the m93cx6-w devices operate within a voltage supply range from 2.5 v to 5.5 v, and the m93cx6-r devices operate within a voltage supply range from 1.8 v to 5.5 v. all these devices operate with a clock frequency of 2 mhz (or less), over an ambient temperature range of -40 c / +85 c. figure 1. logic diagram table 2. memory size versus organization device number of bits number of 8-bit bytes number of 16-bit words m93c86 16384 2048 1024 m93c76 8192 1024 512 m93c66 4096 512 256 m93c56 2048 256 128 m93c46 1024 128 64 ai01928 d v cc m93cx6 v ss c q s org
docid4997 rev 13 7/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx description figure 2. 8-pin package connections (top view) 1. see section 11: package mechanical data for package dimensions, and how to identify pin-1. 2. du = don?t use. the du (do not use) pin does not co ntribute to the normal operation of the device. it is reserved for use by stmicroelectronics during test sequences. the pin may be left unconnected or may be connected to v cc or v ss . table 3. signal names signal name function direction s chip select input d serial data input input q serial data output output c serial clock input org organization select input v cc supply voltage v ss ground v ss q org du c sv cc d ai01929b m93cx6 1 2 3 4 8 7 6 5
connecting to the serial bus m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 8/33 docid4997 rev 13 2 connecting to the serial bus figure 3 shows an example of three memory devices connected to an mcu, on a serial bus. only one device is selected at a time, so only one device drives the serial data output (q) line at a time, the other devices are high impedance. the pull-down resistor r (represented in figure 3 ) ensures that no device is selected if the bus master leaves the s line in the high impedance state. in applications where the bus master may be in a state where all inputs/outputs are high impedance at the same time (for example, if the bus master is reset during the transmission of an instruction), the clock line (c) must be connected to an external pull-down resistor so that, if all inputs/outputs become high impedanc e, the c line is pulled low (while the s line is pulled low): this ensures that c does not become high at the same time as s goes low, and so, that the t slch requirement is met. the typical value of r is 100 k . figure 3. bus master and memory devices on the serial bus ai14377b bus master m93xxx memory device sdo sdi sck cqd s m93xxx memory device cqd s m93xxx memory device cqd s cs3 cs2 cs1 org org org rr r v cc v cc v cc v cc v ss v ss v ss v ss r
docid4997 rev 13 9/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx operating features 3 operating features 3.1 supply voltage (v cc ) 3.1.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied. in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 3.1.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc . during this time, the chip select (s) line is not allowed to float and should be driven to v ss , it is therefore recommended to connect the s line to v ss via a suitable pull-down resistor. the v cc rise time must not vary faster than 1 v/s. 3.1.3 power-up and device reset in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in operating conditions, in section 10: dc and ac parameters ). when v cc passes the por threshold, the device is reset and is in the following state: ? standby power mode ? deselected (assuming that there is a pull-down resistor on the s line) 3.1.4 power-down at power-down (continuous decrease in v cc ), as soon as v cc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any inst ruction sent to it. during power-down, the device must be deselected and in the standby power mode (that is, there should be no internal write cycle in progress).
memory organization m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 10/33 docid4997 rev 13 4 memory organization the m93cx6 memory is organized either as bytes (x8) or as words (x16). if organization select (org) is le ft unconnected (or connected to v cc ) the x16 organization is selected; when organization select (org) is connected to ground (v ss ) the x8 organization is selected. when the m93cx6 is in standby mo de, organization select (org) should be set either to v ss or v cc for minimum power consumption. any voltage between v ss and v cc applied to organization select (org) may increase the standby current.
docid4997 rev 13 11/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx instructions 5 instructions the instruction set of the m93cx6 devices cont ains seven instructions , as summarized in table 4 to table 6 . each instructio n consists of the following parts, as shown in figure 4: read, write, wen, wds sequences : ? each instruction is preceded by a rising edge on chip select inpu t (s) with serial clock (c) being held low. ? a start bit, which is the first ?1? read on se rial data input (d) during the rising edge of serial clock (c). ? two op-code bits, read on serial data input (d) during the rising edge of serial clock (c). (some instructions also use the first two bits of the address to define the op-code). ? the address bits of the byte or word th at is to be accessed. for the m93c46, the address is made up of 6 bits for the x16 org anization or 7 bits for the x8 organization (see table 4 ). for the m93c56 and m93c66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see table 5 ). for the m93c76 and m93c86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see table 6 ). the m93cx6 devices are fabricated in cmos technology and are therefore able to run as slow as 0 hz (static input signals) or as fast as the maximum ratings specified in ?ac characteristics? tables, in section 10: dc and ac parameters . table 4. instruction set for the m93c46 instruction description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address (1) data required clock cycles address (1) data required clock cycles read read data from memory 1 10 a6-a0 q7-q0 a5-a0 q15-q0 write write data to memory 1 01 a6-a0 d7-d0 18 a5-a0 d15-d0 25 wen write enable 1 00 11x xxxx 10 11 xxxx 9 wds write disable 1 00 00x xxxx 10 00 xxxx 9 erase erase byte or word 1 11 a6-a0 10 a5-a0 9 eral erase all memory 1 00 10x xxxx 10 10 xxxx 9 wral write all memory with same data 100 01x xxxx d7-d0 18 01 xxxx d15-d0 25 1. x = don't care bit.
instructions m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 12/33 docid4997 rev 13 table 5. instruction set for the m93c56 and m93c66 instruction description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address (1) (2) data required clock cycles address (1) (3) data required clock cycles read read data from memory 1 10 a8-a0 q7-q0 a7-a0 q15-q0 write write data to memory 1 01 a8-a0 d7-d0 20 a7-a0 d15-d0 27 wen write enable 1 00 1 1xxx xxxx 12 11xx xxxx 11 wds write disable 1 00 0 0xxx xxxx 12 00xx xxxx 11 erase erase byte or word 1 11 a8-a0 12 a7-a0 11 eral erase all memory 100 1 0xxx xxxx 12 10xx xxxx 11 wral write all memory with same data 100 0 1xxx xxxx d7-d0 20 01xx xxxx d15-d0 27 1. x = don't care bit. 2. address bit a8 is not decoded by the m93c56. 3. address bit a7 is not decoded by the m93c56. table 6. instruction set for the m93c76 and m93c86 instruction description start bit op- code x8 origination (org = 0) x16 origination (org = 1) address (1), (2) data required clock cycles address (1) (3) data required clock cycles read read data from memory 1 10 a10-a0 q7-q0 a9-a0 q15-q0 write write data to memory 1 01 a10-a0 d7-d0 22 a9-a0 d15-d0 29 wen write enable 1 00 11x xxxx xxxx 14 11 xxxx xxxx 13 wds write disable 1 00 00x xxxx xxxx 14 00 xxxx xxxx 13 erase erase byte or word 1 11 a10-a0 14 a9-a0 13 eral erase all memory 1 00 10x xxxx xxxx 14 10 xxxx xxxx 13 wral write all memory with same data 100 01x xxxx xxxx d7-d0 22 01 xxxx xxxx d15-d0 29 1. x = don't care bit. 2. address bit a10 is not decoded by the m93c76. 3. address bit a9 is not decoded by the m93c76.
docid4997 rev 13 13/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx instructions 5.1 read data from memory the read data from memory (read) instruction outputs data on serial data output (q). when the instruction is receiv ed, the op-code and address are decoded, and the data from the memory is transferre d to an output shift register. a du mmy 0 bit is output first, followed by the 8-bit byte or 16-bit wo rd, with the most significant bit first. output data changes are triggered by the rising edge of serial clock (c). the m93cx6 automatically increments the internal address register and clocks out the next byte (or word) as long as the chip select input (s) is held high. in th is case, the dummy 0 bit is not output between bytes (or words) and a continuous stream of data can be read (the address counter automatically rolls over to 00h when the highest address is reached). 5.2 erase and write data 5.2.1 write enable and write disable the write enable (wen) instruction enables the future execution of erase or write instructions, and the write disable (wds) inst ruction disables it. when power is first applied, the m93cx6 initializes it self so that erase and write instructions are disabled. after a write enable (wen) instruction has been exec uted, erasing and writing remains enabled until a write disable (wds) instruction is executed, or until v cc falls below the power-on reset threshold voltage. to protect the memory contents from accidental corruption, it is advisable to issue the write disable (wds) in struction after every write cycle. the read data from memory (read) instruction is not af fected by the write enable (wen) or write disable (wds) instructions. 5.2.2 write for the write data to memory (write) instructio n, 8 or 16 data bits follow the op-code and address bits. these form the byte or word that is to be written. as with the other bits, serial data input (d) is sampled on the rising edge of serial clock (c). after the last data bit has been sampled, the chip select input (s) must be taken low before the next rising edge of serial clock (c). if chip select input (s) is brought low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. the completion of the cycle can be detected by monitoring the ready/ busy line, as described la ter in this document. once the write cycle has been started, it is inte rnally self-timed (the ex ternal clock signal on serial clock (c) may be stopped or left running after the start of a write cycle). the write cycle is automatically preceded by an erase cycle, so it is unnecessary to execute an explicit erase instruction before a writ e data to memory (write) instruction.
instructions m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 14/33 docid4997 rev 13 figure 4. read, write, wen, wds sequences 1. for the meanings of an, xn, qn and dn, see table 4 , table 5 and table 6 . ai00878d 1 1 0 an a0 qn q0 data out d s q read s write addr op code 1 0an a0 data in d q op code dn d0 1 busy ready s write enable 1 0xnx0 d op code 1 01 s write disable 1 0xnx0 d op code 0 0 0 check status addr
docid4997 rev 13 15/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx instructions 5.2.3 write all as with the erase all memory (eral) instruct ion, the format of the write all memory with same data (wral) instruction requires that a dummy address be provided. as with the write data to memory (write) instruction, th e format of the write all memory with same data (wral) instruction requires that an 8-bit data byte, or 16-bit data word, be provided. this value is written to all the addresses of the memory device. the co mpletion of the cycle can be detected by monitoring the ready/ busy line, as described next. figure 5. wral sequence 1. for the meanings of xn and dn, please see table 4 , table 5 and table 6 . ai00880c s write all data in d q addr op code dn d0 busy ready check status 1 0 0 0 1 xn x0
instructions m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 16/33 docid4997 rev 13 5.2.4 erase byte or word the erase byte or word (erase) instruction sets the bits of the addressed memory byte (or word) to 1. once the address has been correctly decoded, the falling edge of the chip select input (s) starts the self-timed eras e cycle. the completion of the cycle can be detected by monitoring the ready/ busy line, as described in section 6: ready/busy status . figure 6. erase, eral sequences 1. for the meanings of an and xn, please see table 4 , table 5 and table 6 . 5.2.5 erase all the erase all memory (eral) instruction erases the whole memory (all memory bits are set to 1). the format of the instruction requires that a dummy address be provided. the erase cycle is conducted in the same way as the erase instructi on (erase). the completion of the cycle can be detected by monitoring the ready/ busy line, as described in section 6: ready/busy status . ai00879b s erase 1 1 d q addr op code 1 busy ready check status s erase all 1 0 d q op code 1 busy ready check status 0 0 an a0 xn x0 addr
docid4997 rev 13 17/33 m93c86xx m93c76xx m93c66xx m93c 56xx m93c46xx ready/busy status 6 ready/busy status while the write or erase cycle is underw ay, for a write, eras e, wral or eral instruction, the busy signal (q=0) is returned whenever chip select inpu t (s) is driven high. (please note, though, that there is an initial delay, of t slsh , before this status information becomes available). in this state, the m93cx6 ignores any data on the bus. when the write cycle is completed, and chip select input (s) is driven high, the ready signal (q=1) indicates that the m93cx6 is re ady to receive the next instruction. serial data output (q) remains set to 1 until the chip select input (s) is brought low or until a new start bit is decoded. 7 initial delivery state the device is delivered with all bits in the me mory array set to 1 (each byte contains ffh).
clock pulse counter m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 18/33 docid4997 rev 13 8 clock pulse counter in a noisy environment, the number of pulses received on serial clock (c) may be greater than the number delivered by the master (the microcontroller). this can lead to a misalignment of the instruction of one or more bits (as shown in figure 7 ) and may lead to the writing of erroneous data at an erroneous address. to avoid this problem, the m93cx6 has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the chip se lect input (s). if the number of clock pulses received is not the number expected, the write, erase, er al or wral instruction is aborted, and the contents of the memory are not modified. the number of clock cycles expected for ea ch instruction, and for each member of the m93cx6 family, are summarized in table 4: instruction set for the m93c46 to table 6: instruction set for the m93c76 and m93c86 . for example, a write data to memory (write) instruction on the m93c56 (or m93c66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of chip select input (s). that is: 1 start bit + 2 op-code bits + 9 address bits + 8 data bits figure 7. write sequence with one clock glitch ai01395 s an-1 c d write start d0 "1" "0" an glitch an-2 address and data are shifted by one bit
docid4997 rev 13 19/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx maximum rating 9 maximum rating stressing the device outside the ratings liste d in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions outside those indicat ed in the operating sections of this specification, is not im plied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability. table 7. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering pdip 260 (1) 1. t lead max must not be applied for more than 10 s. other packages see note (2) 2. compliant with jedec std j-std-020d (for smal l body, sn-pb or pb-free assembly), the st ecopack? 7191395 specification, and the europ ean directive on restrictions of hazardous substances (rohs) 2011/65/eu. c v out output range (q = v oh or hi-z) ?0.50 v cc +0.5 v v in input range ?0.50 v cc +1 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) (3) 3. positive and negative pulses applied on pin pairs, according to the aec-q100-002 (compliant with jedec std jesd22-a114, c1 = 100pf, r1 = 1500 , r2 = 500 ). 4000 v
dc and ac parameters m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 20/33 docid4997 rev 13 10 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check th at the operating conditions in their circuit match the measurement conditions wh en relying on the quoted parameters. table 8. operating conditions (m93cx6) symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature ?40 85 c table 9. operating conditions (m93cx6-w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 85 c table 10. operating conditions (m93cx6-r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 11. ac measurement conditions (m93cx6) symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input voltage levels 0.4 v to 2.4 v v input timing reference voltages 1.0 v and 2.0 v v output timing reference voltages 0.8 v and 2.0 v v table 12. ac measurement conditions (m93cx6-w and m93cx6-r) symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input voltage levels 0.2 v cc to 0.8 v cc v input timing reference voltages 0.3 v cc to 0.7 v cc v output timing reference voltages 0.3 v cc to 0.7 v cc v
docid4997 rev 13 21/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx dc and ac parameters figure 8. ac testing input output waveforms table 13. capacitance symbol parameter test condition (1) 1. sampled only, not 100% tested, at t a = 25 c and a frequency of 1 mhz. min max unit c out output capacitance v out = 0v 5 pf c in input capacitance v in = 0v 5 pf table 14. dc characteristics (m93cx6, device grade 6) symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current v cc = 5 v, s = v ih , f = 2 mhz, q = open 2 ma i cc1 supply current (standby) v cc = 5 v, s = v ss , c = v ss , org = v ss or v cc , pin7 = v cc , v ss or hi-z 15 a v il (1) 1. please note that the input and output levels defined in this table are compatible with ttl logic levels and are not fully compatible with cmos levels (as defined in table 15 ). input low voltage v cc = 5 v 10% ?0.45 0.8 v v ih (1) input high voltage v cc = 5 v 10% 2 v cc + 1 v v ol (1) output low voltage v cc = 5 v, i ol = 2.1 ma 0.4 v v oh (1) output high voltage v cc = 5 v, i oh = ?400 a 0.8v cc v ms19788v2 2.4v 0.4v 2.0v 0.8v 2v 1v input 0.8v cc 0.2v cc 0.7v cc 0.3v cc m93cxx output input voltage levels input and output timing reference levels input voltage levels m93cxx-w and m93cxx-r input and output timing reference levels
dc and ac parameters m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 22/33 docid4997 rev 13 table 15. dc characteristics (m93cx6-w, device grade 6) symbol parameter test condition min. max. unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5 v, s = v ih , f = 2 mhz, q = open 2 ma v cc = 2.5 v, s = v ih , f = 2 mhz, q = open 1 ma i cc1 supply current (standby) v cc = 2.5 v, s = v ss , c = v ss , org = v ss or v cc , pin7 = v cc , v ss or hi-z 5 a v il input low voltage (d, c, s) ?0.45 0.2 v cc v v ih input high voltage (d, c, s) 0.7 v cc v cc + 1 v v ol output low voltage (q) v cc = 5 v, i ol = 2.1 ma 0.4 v v cc = 2.5 v, i ol = 100 a 0.2 v v oh output high voltage (q) v cc = 5 v, i oh = ?400 a 0.8 v cc v v cc = 2.5 v, i oh = ?100 a v cc ?0.2 v table 16. dc characteristics (m93cx6-r) symbol parameter test condition min. (1) 1. this product is under development. for more information, please contact your nearest st sales office. max. (1) unit i li input leakage current 0v v in v cc 2.5 a i lo output leakage current 0v v out v cc , q in hi-z 2.5 a i cc supply current (cmos inputs) v cc = 5 v, s = v ih , f = 2 mhz, q = open 2 ma v cc = 1.8 v, s = v ih , f = 1 mhz, q = open 1 ma i cc1 supply current (standby) v cc = 1.8 v, s = v ss , c = v ss , org = v ss or v cc , pin7 = v cc , v ss or hi-z 2 a v il input low voltage (d, c, s) ?0.45 0.2 v cc v v ih input high voltage (d, c, s) 0.8 v cc v cc + 1 v v ol output low voltage (q) v cc = 1.8 v, i ol = 100 a 0.2 v v oh output high voltage (q) v cc = 1.8 v, i oh = ?100 a v cc ?0.2 v
docid4997 rev 13 23/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx dc and ac parameters table 17. ac characteristics (m93cx6, device grade 6) test conditions specified in table 8 and table 11 symbol alt. parameter min. max. unit f c f sk clock frequency d.c. 2 mhz t slch chip select low to clock high 50 ns t shch t css chip select setup time m93c46, m93c56, m93c66 50 ns chip select setup time m93c76, m93c86 50 ns t slsh (1) 1. chip select input (s) must be brought low for a minimum of t slsh between consecutive instruction cycles. t cs chip select low to chip select high 200 ns t chcl (2) 2. t chcl + t clch 1 / f c . t skh clock high time 200 ns t clch (2) t skl clock low time 200 ns t dvch t dis data in setup time 50 ns t chdx t dih data in hold time 50 ns t clsh t sks clock setup time (re lative to s) 50 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 200 ns t slqz t df chip select low to output hi-z 100 ns t chql t pd0 delay to output low 200 ns t chqv t pd1 delay to output valid 200 ns t w t wp erase or write cycle time 5 ms
dc and ac parameters m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 24/33 docid4997 rev 13 table 18. ac characteristics (m93cx6-w, device grade 6) test conditions specified in table 9 and table 12 symbol alt. parameter min. max. unit f c f sk clock frequency d.c. 2 mhz t slch chip select low to clock high 50 ns t shch t css chip select setup time 50 ns t slsh (1) 1. chip select input (s) must be brought low for a minimum of t slsh between consecutive instruction cycles. t cs chip select low to chip select high 200 ns t chcl (2) 2. t chcl + t clch 1 / f c . t skh clock high time 200 ns t clch (2) t skl clock low time 200 ns t dvch t dis data in setup time 50 ns t chdx t dih data in hold time 50 ns t clsh t sks clock setup time (relative to s) 50 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 200 ns t slqz t df chip select low to output hi-z 100 ns t chql t pd0 delay to output low 200 ns t chqv t pd1 delay to output valid 200 ns t w t wp erase or write cycle time 5 ms
docid4997 rev 13 25/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx dc and ac parameters figure 9. synchronous timing (start and op-code input) table 19. ac characteristics (m93cx6-r) test conditions specified in table 10 and table 12 symbol alt. parameter min. (1) 1. this product is under development. for more information, please contact your nearest st sales office. max. (1) unit f c f sk clock frequency d.c. 1 mhz t slch chip select low to clock high 250 ns t shch t css chip select setup time 50 ns t slsh (2) 2. chip select input (s) must be brought low for a minimum of t slsh between consecutive instruction cycles. t cs chip select low to chip select high 250 ns t chcl (3) 3. t chcl + t clch 1 / f c . t skh clock high time 250 ns t clch (3) t skl clock low time 250 ns t dvch t dis data in setup time 100 ns t chdx t dih data in hold time 100 ns t clsh t sks clock setup time (relative to s) 100 ns t clsl t csh chip select hold time 0 ns t shqv t sv chip select to ready/busy status 400 ns t slqz t df chip select low to output hi-z 200 ns t chql t pd0 delay to output low 400 ns t chqv t pd1 delay to output valid 400 ns t w t wp erase or write cycle time 10 ms ai01428 c op code op code start s d op code input start tdvch tshch tclsh tchcl tclch tchdx
dc and ac parameters m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 26/33 docid4997 rev 13 figure 10. synchronous timing (read or write) figure 11. synchronous timing (read or write) ai00820c c d q address input hi-z tdvch tclsl a0 s data output tchqv tchdx tchql an tslsh tslqz q15/q7 q0 ai01429 c d q address/data input hi-z tdvch tslch a0/d0 s write cycle tslsh tchdx an tclsl tslqz busy tshqv tw ready
docid4997 rev 13 27/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx package mechanical data 11 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their le vel of environmental compliance. ecopack? specifications, grade definitions a nd product status are available at: www.st.com . ecopack? is an st trademark . figure 12. pdip8 ? 8 lead plastic dual in -line package, 300 mils body width, package outline 1. drawing is not to scale. table 20. pdip8 ? 8 lead plastic dual in-line package, 300 mils body width, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a - - 5.33 - - 0.2098 a1 - 0.38 - - 0.015 - a2 3.3 2.92 4.95 0.1299 0.115 0.1949 b 0.46 0.36 0.56 0.0 181 0.0142 0.022 b2 1.52 1.14 1.78 0.0598 0.0449 0.0701 c 0.25 0.2 0.36 0.0098 0.0079 0.0142 d 9.27 9.02 10.16 0.365 0.3551 0.4 e 7.87 7.62 8.26 0.3098 0.3 0.3252 e1 6.35 6.1 7.11 0.25 0.2402 0.2799 e 2.54 - - 0.1 - - ea 7.62 - - 0.3 - - eb - - 10.92 - - 0.4299 l 3.3 2.92 3.81 0.1299 0.115 0.15 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
package mechanical data m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 28/33 docid4997 rev 13 figure 13. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 21. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a - - 1.75 - - 0.0689 a1 - 0.1 0.25 - 0.0039 0.0098 a2 - 1.25 - - 0.0492 - b - 0.28 0.48 - 0.011 0.0189 c - 0.17 0.23 - 0.0067 0.0091 ccc - - 0.1 - - 0.0039 d 4.9 4.8 5 0.1929 0.189 0.1969 e 6 5.8 6.2 0.2362 0.2283 0.2441 e1 3.9 3.8 4 0.1535 0.1496 0.1575 e 1.27 - - 0.05 - - h - 0.25 0.5 - 0.0098 0.0197 k-08-08 l - 0.4 1.27 - 0.0157 0.05 l1 1.04 - - 0.0409 - - so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
docid4997 rev 13 29/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx package mechanical data figure 14. ufdfpn8 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline 1. drawing is not to scale. 2. the central pad (area e2 by d2 in the above illustration) is pulled, internally, to v ss . it must not be allowed to be connected to any other voltage or signal line on the pcb, for example during the soldering process. 3. the circle in the top view of the package indicates the position of pin 1. table 22. ufdfpn8 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to four decimal digits. typ min max typ min max a 0.550 0.450 0.600 0.0217 0.0177 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 d 2.000 1.900 2.100 0.0787 0.0748 0.0827 d2 (rev mc) - 1.200 1.600 - 0.0472 0.0630 e 3.000 2.900 3.100 0.1181 0.1142 0.1220 e2 (rev mc) - 1.200 1.600 - 0.0472 0.0630 e 0.500 - - 0.0197 - - k (rev mc) - 0.300 - - 0.0118 - l - 0.300 0.500 - 0.0118 0.0197 l1 - - 0.150 - - 0.0059 l3 - 0.300 - - 0.0118 - eee (2) 2. applied for exposed die paddle and terminal s. exclude embedding part of exposed die paddle from measuring. - 0.080 - - 0.0031 - d e zw_meev2 a a1 eee l1 e b d2 l e2 l3 pin 1 k
package mechanical data m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 30/33 docid4997 rev 13 figure 15. tssop8 ? 8 lead thin shri nk small outline, package outline 1. drawing is not to scale. table 23. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a - - 1.2 - - 0.0472 a1 - 0.05 0.15 - 0.002 0.0059 a2 1 0.8 1.05 0.0394 0.0315 0.0413 b - 0.19 0.3 - 0.0075 0.0118 c - 0.09 0.2 - 0.0035 0.0079 cp - - 0.1 - - 0.0039 d 3 2.9 3.1 0.1181 0.1142 0.122 e 0.65 - - 0.0256 - - e 6.4 6.2 6.6 0.252 0.2441 0.2598 e1 4.4 4.3 4.5 0.1732 0.1693 0.1772 l 0.6 0.45 0.75 0.0236 0.0177 0.0295 l1 1 - - 0.0394 - - -08-08 n (pin number) 8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
docid4997 rev 13 31/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx part numbering 12 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 24. ordering information scheme example: m93c86 ? w mn 6 t p device type m93 = microwire serial eeprom device function 86 = 16 kbit (2048 x 8) 76 = 8 kbit (1024 x 8) 66 = 4 kbit (512 x 8) 56 = 2 kbit (256 x 8) 46 = 1 kbit (128 x 8) operating voltage blank = v cc = 4.5 to 5.5 v w = v cc = 2.5 to 5.5 v r = v cc = 1.8 to 5.5 v package bn = pdip8 mn = so8 (150 mils width) mc = ufdfpn8 2 x 3 mm (mlp8) dw = tssop8 (169 mils width) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow packing blank = standard packing t = tape and reel packing plating technology p or g = ecopack ? (rohs compliant)
revision history m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx 32/33 docid4997 rev 13 13 revision history table 25. document revision history date revision changes 01-apr-2010 9 modified footnote in table 14 and table 15 on page 23 updated figure 14: ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline and table 22: ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data 29-apr-2010 10 updated figure 31: available m93c66-x products (package, voltage range, temperature grade) ufdfpn option. 12-apr-2011 11 updated table 7: absolute maximum ratings , mlp8 package data in section 12: package mechanical data and process data in section 9: clock pulse counter . deleted table 29: available m93c46-x products (package, voltage range, temperature grade) , table 30: available m93c56-x products (package, voltage range, temperature grade) , table 31: available m93c66-x products (package, voltage range, temperature grade) , table 32: available m93c76-x products (package, voltage range, temperature grade) and table 33: available m93c86-x products (package, voltage range, temperature grade) . 05-oct-2011 12 updated table 1: device summary and table 8: operating conditions (m93cx6) . modified footnote 2 in table 7 . 23-apr-2013 13 document reformatted. updated: ? part number names ? table 1: device summary and package figure on cover page ? section 1: description ? introductory paragraph in section 9: maximum rating ? note (2) under table 7: absolute maximum ratings ? table 8: operating conditions (m93cx6) and table 9: operating conditions (m93cx6-w) ? introductory paragraph in section 11: package mechanical data ? figure 14: ufdfpn8 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline and table 22: ufdfpn8 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data ? table 24: ordering information scheme renamed: ? figure 2: 8-pin package connections (top view) ? table 17: ac characteristics (m93cx6, device grade 6) deleted: ? section: common i/o operation ? table: dc characteristics (m93cx6, device grade 3), table: dc characteristics (m93cx6-w, device grade 3), and table: ac characteristics (m93cx6-w, device grade 3)
docid4997 rev 13 33/33 m93c86xx m93c76xx m93c66xx m93c56xx m93c46xx please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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